Cypress Semiconductor /psoc63 /GPIO /PRT[5] /CFG_OUT

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Interpret as CFG_OUT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLOW0)SLOW0 0 (SLOW1)SLOW1 0 (SLOW2)SLOW2 0 (SLOW3)SLOW3 0 (SLOW4)SLOW4 0 (SLOW5)SLOW5 0 (SLOW6)SLOW6 0 (SLOW7)SLOW7 0 (FULL_DRIVE)DRIVE_SEL0 0DRIVE_SEL1 0DRIVE_SEL2 0DRIVE_SEL3 0DRIVE_SEL4 0DRIVE_SEL5 0DRIVE_SEL6 0DRIVE_SEL7

DRIVE_SEL0=FULL_DRIVE

Description

Port output buffer configuration register

Fields

SLOW0

Enables slow slew rate for IO pin 0 ‘0’: Fast slew rate ‘1’: Slow slew rate

SLOW1

Enables slow slew rate for IO pin 1

SLOW2

Enables slow slew rate for IO pin 2

SLOW3

Enables slow slew rate for IO pin 3

SLOW4

Enables slow slew rate for IO pin 4

SLOW5

Enables slow slew rate for IO pin 5

SLOW6

Enables slow slew rate for IO pin 6

SLOW7

Enables slow slew rate for IO pin 7

DRIVE_SEL0

Sets the GPIO drive strength for IO pin 0

0 (FULL_DRIVE): Full drive strength: GPIO drives current at its max rated spec.

1 (ONE_HALF_DRIVE): 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec

2 (ONE_QUARTER_DRIVE): 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.

3 (ONE_EIGHTH_DRIVE): 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.

DRIVE_SEL1

Sets the GPIO drive strength for IO pin 1

DRIVE_SEL2

Sets the GPIO drive strength for IO pin 2

DRIVE_SEL3

Sets the GPIO drive strength for IO pin 3

DRIVE_SEL4

Sets the GPIO drive strength for IO pin 4

DRIVE_SEL5

Sets the GPIO drive strength for IO pin 5

DRIVE_SEL6

Sets the GPIO drive strength for IO pin 6

DRIVE_SEL7

Sets the GPIO drive strength for IO pin 7

Links

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